1. Field of the Invention
The present invention is generally related to latch timing circuits for integrated circuits.
2. Description of Background Art
Transparent latch timing circuits are commonly used in integrated circuits to regulate the flow of logical data signals in each logical path. Referring to FIG. 1, a common latch timing design is a two-phase non-overlapping latch timing circuit 100. During a first portion of the clock cycle, the L1 latch (es) are transparent, allowing a data input to enter the latch, such as into a logic unit 130. During the first clock phase, the L2 latch(es) are closed. During a second portion of the clock cycle, the L1 latches close and the L2 latches become transparent. The sequence of non-overlapping clock phases has several advantages. One benefit is that it prevents a race condition from occurring in outputs fed back through a second logic path 150. This makes the two-phase non-overlapping latch timing circuit robust to design shortcomings and insensitive to manufacturing factors that affect the timing of logical signals in an integrated circuit. Additionally, a two-phase non-overlapping latch timing circuit facilitates testing and debugging using a scan chain and/or other evaluation techniques.
A drawback of the conventional two-phase latch timing circuit 100 is that it consumes more clock power than desired. Some studies indicate that the clock power in a high performance microprocessor can be as high as 70% of total chip power consumption, although 30%-40% is a more typical range for a microprocessor utilizing a conventional two-phase latch timing architecture.
What is desired is a latch timing circuit that has the desirable benefits of a two-phase latch timing circuit but which also permits a reduction in clock power consumption.
A multimode latch timing circuit is disclosed having at least two modes of operation. The latch timing circuit has two sets of timing latches for controlling the flow of data in a logical path. In one mode of operation, the latch timing circuit operates as a two-phase transparent latch timing circuit with the first set of latches being driven by a first phase clock signal and the second set of latches being driven by a second phase clock signal. In a reduced clock power mode of operation, the first set of latches may be held in a transparent state with a constant bias voltage, reducing clock power consumption by up to half. In long paths, the first set of latches may be held in a transparent state with the second set of latches driven by the second phase clock signal. In short paths, the first set of latches may be held in a transparent state with the second set of latches driven by a second phase clock signal comprising short duty cycle pulses with a pulse width selected to prevent a race condition. The first mode of operation may be used during testing and bring up of an integrated circuit incorporating the latch timing circuit. If the timing delays of the integrated circuit permit operation in the reduced clock power mode of operation, the integrated circuit may be programmed to operate in the reduced clock power mode in one or more logical paths.
In one embodiment, the first set of latches is coupled to a first clock driver and the second set of latches is coupled to a second clock driver. In one embodiment, each clock driver comprises a buffer circuit acting responsive to the output of a logical circuit receiving the master clock signal and at least one control signal.